Referring now to FIG. 11, an etch is performed to define the length of the vertical-surrounding-gate of the transistor. Once again, using hard mask 81, the STI oxide 61 and the silicon substrate 60 are etched down to a desired depth starting at the base of nitride spacers 100 to increase the length of silicon pillars 90 and to establish the channel length 110 of the completed vertical-surrounding-gate transistor. Once the partial etch of the silicon pillars is performed and the nitride spacers formed thereon using the process steps described in FIGS. 9 and 10, the subsequent etch allows for an effective and reliable method to establish the desired channel length and height of the vertical-surrounding-gate transistor.
The vertical-surrounding-gate field effect transistors of the present invention as constructed in semiconductor devices may be applied to a semiconductor system, such as the one depicted in FIG. 21. FIG. 21 represents a general block diagram of a semiconductor system, the general operation of which is known to one skilled in the art, the semiconductor system comprising a processor 212 and a memory device 213 showing the basic sections of a memory integrated circuit, such as row and column address buffers 214 and 215, row and column decoders, 216 and 217, sense amplifiers 218, memory array 219 and data input/output 220, which are manipulated by control/timing signals from the processor through control 221.
The overhead view of FIG. 1 shows a series of circular nitride hard masks 11 defining columns of vertical silicon pillars separated by shallow trench isolation 12. A cross-section taken through line 1-1′ of FIG. 1 is depicted in FIG. 2. As seen in FIG. 2, the vertical silicon pillars 20 are formed by etching into the silicon substrate 10 by using the nitride hard mask 11 as an etching guide. Shallow trench isolation 12 is formed between each column of silicon pillars.
As shown in FIG. 3, a conformal gate dielectric 30 is formed on the substrate surface such that it coats the horizontal surface of silicon substrate 10, the shallow trench isolation 12, the vertical sidewalls of the silicon pillars 20 and the nitride hard mask 11.
As shown in FIG. 4, a polysilicon 40 is deposited to fill the spaces between the silicon pillars 20. Then the polysilicon 40 is planarized along with a top portion of the nitride hard mask 11.
As shown in FIG. 5, the polysilicon 40 is recessed to a designed thickness, which will expose an upper portion of the gate dielectric 30 as well as define the gate channel length of the vertical gated transistor. This approach has two main potential problems in that the recessing of polysilicon 40, typically by a plasma etch, has the tendency to damage the gate dielectric/polysilicon interface and the plasma etch causes unavoidable round corners 50 above the major horizontal surface of the vertical-surrounding-gate at the gate dielectric/polysilicon interface. These rounded corners 50 will increase gate channel length variation across the silicon substrate 10. Furthermore any misalignment between the gate polysilicon pattern and the silicon pillar 20 will increase the serial resistance of each transistor structure along with potential gate damage due to exposing the silicon channel.
The present invention describes a vertical-surrounding gate field effect transistor formed by a method to define a gate channel length for a vertical-surrounding gate field effect transistor with self-aligning features that addresses the above challenges, the method disclosed herein for use in the manufacture of semiconductor devices or assemblies, which will become apparent to those skilled in the art from the following disclosure.